View ISL55100AEVAL3Z_8388639.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 datasheet quad 18v pin electronics driver/window comparator isl55100a the isl55100a is a quad pin dr iver and window comparator fabricated in a wide voltage cmos process. it is designed specifically for test during burn in (tdbi) applications, where cost, functional density and power are all at a premium. this ic incorporates four channels of programmable drivers and window comparators into a small 72 ld qfn package. each channel has independent driver levels, data and high impedance control. each receiver has dual comparators, which provide high and low threshold levels. the isl55100a uses differential mode digital inputs and can therefore mate directly with lvds or cml outputs. single-ended logic families are handled by connecting one of the digital input pins to an appropriate threshold voltage (e.g., 1.4v for ttl compatibility). the comparator outputs are single-ended and the output levels are user defined to mate directly with any digital technology. the 18v driver output and receiver input ranges allow this device to interface directly with ttl, ecl, cmos (3v, 5v and 7v), lvcmos and custom level circuitry, as well as the high voltage (super voltage) level required for many special test modes for flash devices. features ? low driver output resistance -r out maximum: isl55100a 7.0 ?18v i/o range ? 50mhz operation ? 4-channel driver/receiver pairs with per pin flexibility ? dual level - per pin - input thresholds ? differential or single-ended digital inputs ? user defined comparator output levels ? low channel-to-channel timing skew ? small footprint (72 ld qfn) ? pb-free (rohs compliant) applications ?burn in ate ? wafer level flash memory test ?lcd panel test ?low cost ate ? instrumentation ?emulation ? device programmers functional block diagram cva(0:3) cvb(0:3) vinp(0:3) qa(0:3) comp high data-(0:3) drven+(0:3) data+(0:3) vh(0:3) vl(0:3) comp low v cc v ee comp high comp low v cc v ee qb(0:3) quad - dual level comparator - receivers dout(0:3) drven-(0:3) quad - wide range, low rout, tri-stateable - drivers + - + - + - + - december 4, 2014 fn7486.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2005, 2008, 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl55100a 2 fn7486.3 december 4, 2014 submit document feedback ordering information part number ( notes 1 , 2 , 3 )part marking temp. range (c) package (rohs compliant) pkg. dwg. # isl55100airz isl55100 airz -40 to +85 72 ld qfn l72.10x10 ISL55100AEVAL3Z evaluation board notes: 1. add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see product information page for isl55100a for more information on msl, please see tech brief tb363 . pin configuration isl55100a (72 ld qfn) top view drv en+ 0 drv en- 0 qa 0 qb 0 72 71 70 69 68 67 66 65 64 63 62 61 vee vcc nc nc nc nc v ee v cc 60 59 v ee v cc v ext vh 0 dout 0 nc vl 0 vh 1 dout 1 nc vl 1 vh 2 dout 2 nc vl 2 vh 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 54 53 52 51 50 49 48 47 46 45 44 43 42 41 data+ 0 data- 0 qa 1 qb 1 drv en+ 1 drv en- 1 data+ 1 data- 1 qa 2 qb 2 drv en+ 2 drv en- 2 data+ 2 data- 2 19 20 21 22 23 24 25 26 27 28 29 30 31 32 data+ 3 data- 3 cva 0 vinp 0 cvb 0 comp high comp low v ee v cc cva 1 vinp 1 cvb 1 cva 2 vinp 2 15 16 17 18 qa 3 qb 3 drv en+ 3 drv en- 3 33 34 35 36 cvb 2 cva 3 cvb 3 vinp 3 dout 3 nc vl 3 lowswing 40 39 38 37 58 57 nc nc 56 55 nc nc ep
isl55100a 3 fn7486.3 december 4, 2014 submit document feedback pin descriptions pin name function data+(0:3) positive differential digital input that dete rmines the driver output state when it is enabled. data-(0:3) negative differential digital input that dete rmines the driver output state when it is enabled. drv en +(0:3) positive differential digital input that enables or disables the corresponding driver. drv en -(0:3) negative differential digital input that enables or disables the corresponding driver. qa (0:3) comparator digital outputs. qa(x ) is high when vinp(x) exceeds cva(x). qb (0:3) comparator digital outputs. qb(x ) is high when vinp(x) exceeds cvb(x). dout (0:3) driver outputs. vinp (0:3) comparator inputs. vh (0:3) unbuffered analog inputs that set ea ch individual driver?s ?high? voltage level. vl (0:3) unbuffered analog inputs that set each individual driv er?s ?low? voltage level. vl must be a lower voltage than vh. nc no internal connection. cva (0:3) analog inputs that set the threshold for the corresponding channel?s a comparators. cvb (0:3) analog inputs that set the threshold for the corresponding channel?s b comparators. comp hi supply voltage, unbuffered input that sets the high outp ut level of all comparators. must be greater than comp lo. comp lo supply voltage, unbuffered input that sets the low outp ut level of all comparators. must be less than comp hi. v cc positive power supply (5% tolerance). v ee negative power supply (5% tolerance). this is also the po tential of the exposed thermal pad on the package bottom. v ext external 5.5vdc power supply (5.5vdc to 6.0vdc as referenced to v ee , not gnd. recommended v ext = 5.5v) for internal logic. connect pin to v ee when not using an external supply. lowswing input that selects driver output configurations optimized to yield minimum overshoots for low level swings (vh < v ee +5v), or optimized for large output swings. connect lowswing to v ee to select low swing circuitry, or connect it to v cc to select high swing circuitry. ep qfn package exposed thermal pad; connect to v ee . truth tables drivers inputs output data drv en dout x + > - hi - z + > - + < - vh + < - + < - vl x = don?t care receivers input outputs vinp qa qb cvb 0 1 >cva cva >cvb 1 1
isl55100a 4 fn7486.3 december 4, 2014 submit document feedback absolute maximum rating s thermal information v cc to v ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 19v v ext to v ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v input voltages data, drv en , cvx, vh, vl, vinp, compx, lowswing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v ee - 0.5v) to (v cc + 0.5v) output voltages dout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v ee - 0.5v) to (vh + 0.5v) qx . . . . . . . . . . . . . . . . . . . . . (comp low - 0.5v) to (comp high + 0.5v) thermal resistance (typical, notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 72 ld qfn package . . . . . . . . . . . . . . . . . . . 23 2.0 maximum junction temperature (plastic package) . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. device temperature is closely tied to data-rates, driver loads and overall pin activity. review ? power dissipation considerations ? on page 9 for more information. recommended operating conditions parameter symbol min ( note 13 )typ max ( note 13 )units device power-(v ext = v ee ) v ext not used v cc - v ee 12 ( note 10 )15 18 v device power-(v ext = v ee + 5.5v) v cc - v ee 9 ( note 10 )15 18 v v ext optional external logic power v ext - v ee 5.5 ( note 10 ) 5.75 6.0 v driver output high rail v h v ee + 1 - v cc - 0.5 v driver output low rail v l v ee + 0.5 - v ee + 6 v comparator output high rail comp-high v ee + 1 - v cc - 0.5 v comparator output low rail comp-low v ee + 0.5 - v ee + 6 v ambient temperature t a -40 - +85 c junction temperature t j - - +150 c electrical specifications test conditions: v cc = 12v, v ee = -3v, vh = 6v, vl = 0v, comp-high = 5v, comp-low = 0v, v 5v = v ee and lowswing = v cc . parameter symbol test conditions min typ max units driver dc characteristics isl55100a output resistance r outd i o = 200ma, data not toggling 3 4.5 7.0 isl55100a dc output current i outd per individual driver 200 - - ma isl55100a ac output current ( note 6 )i outdac per individual driver - 1.0 - a isl55100a minimum output swing v omin v h = 200mv, v l = 0v 185 - - mv disabled hiz leakage current hiz v out = v cc with v h = v l + v ee or v out = vee with v h = v l = v cc -1 0 1 a driver timing characteristics data ? to dout propagation delay t pd lowswing disabled ( note 9 )81216ns lowswing enabled ( note 9 )91317ns driver timing skew, all edges ( note 7 ) - <1 - ns disable (hiz) time t dis dvren ? transition from enable to disable 16 18 26 ns
isl55100a 5 fn7486.3 december 4, 2014 submit document feedback enable time t en dvren ? transition from disable to enable: lowswing disabled ( note 9 ) 13 15 23 ns dvren ? transition from disable to enable: lowswing enabled ( note 9 ) 13 18 23 ns isl55100a rise/fall times ( note 7 )t r , t f 100pf load ? v = 0.4v (20% to 80%) - 2.5 - ns ? v = 1v (20% to 80%) - 2.5 - ns ? v = 5v (10% to 90%) - 2.5 - ns ? v = 10v (10% to 90%) - 2.5 - ns ? v = 14v (10% to 90%) - 2.5 - ns isl55100a rise/fall times ( note 7 )t r , t f 1000pf load ? v = 1v (20% to 80%) - 8.0 - ns ? v = 5v (10% to 90%) - 10.0 - ns ? v = 10v (10% to 90%) - 14.0 - ns isl55100a maximum toggle frequency fmaxd no load, 50% symmetry 50 65 - mhz isl55100a min driver pulse width t widd standard load, 1k/100pf ( note 8 )-7.7 ? ns isl55100a overshoot lowswing mode ( note 7 ) os lowswing enabled, (vh - vl < 2v) - 20mv+ 10% of output swing -% ? v receiver dc characteristics input offset voltage v os cva = cvb = 1.5v -50 - 50 mv input bias current i bias v inp - cv (a/b) = 5v - 10 30 na output resistance r outr 18 25 35 receiver timing characteristics propagation delay t pp 71218 ns maximum operating frequency f maxr under no load, pwout symmetry 50% 50 65 - mhz minimum pulse width t widr -7.7 - ns rcvr channel-to-channel skew ( note 7 ) - <1 - ns digital inputs differential input high voltage v diffh v dig+ - v dig- 200 - - mv differential input low voltage v diffl v dig+ - v dig- - - -200 mv input current i in v in = v cc or v ee -50 0 50 na common mode input voltage range v cm v diffl > v diffh - 0.2v v cc - 5v v v diffh < v diffl + 0.2v v ee + 0.2v - - v power supplies, driver/receiver static conditions v ext = v ee, external logic power option not used . ( notes 10 , 11 ) positive supply current i cc v cc = v h = 12v, v ee = v l = -3v, v ext =v ee , outputs unloaded -6585 ma negative supply current i ee v cc = v h = 12v, v ee = v l = -3v, v ext =v ee , outputs unloaded -85 -65 - ma v ext supply current i ext v cc = v h = 12, v ee = v l = -3v, v ext =v ee , outputs unloaded -<1 - ma power supplies, driver/receiver static conditions v ext = v ee + 5.5v, external logic power option used . ( notes 11 , 12 ) positive supply current i cc v cc = v h = 12v, v ee = v l = -3v, v ext =v ee + 5.5v, outputs unloaded -3550 ma electrical specifications test conditions: v cc = 12v, v ee = -3v, vh = 6v, vl = 0v, comp-high = 5v, comp-low = 0v, v 5v = v ee and lowswing = v cc . (continued) parameter symbol test conditions min typ max units
isl55100a 6 fn7486.3 december 4, 2014 submit document feedback negative supply current i ee v cc = v h = 12v, v ee = v l = -3v, v ext =v ee + 5.5v, outputs unloaded -50 -35 - ma v ext supply current i ext v cc = v h = 12, v ee = v l = -3v, v ext =v ee + 5.5v, outputs unloaded -2540 ma notes: 7. lab characterization, room temp, timing parameters matched st imulus/loads, channel to channel skew < 500ps, 1ns max by design . 8. measured across 100pf/1k lump sum load + 15pf pcb/scope probe. capacitor and resist or surface mount/stacked ~0.5inch from pin . 9. to enable lowswing , connect lowswing to v ee and keep vh < v ee + 5. to disable lowswing , connect it to v cc . 10. when v ext is connected to v ee (external device power not used) then the minimum v cc - v ee is 12v. when v ext is connected to an external 5.5v supply, then the minimum v cc - v ee voltage is 9.0v. recommended v ext = 5.5v as referenced to v ee . 11. i cc and i ee values are based on static conditions and will increase with pattern rates. i cc and i ee reach 400ma to 500ma at maximum data rates (provided sufficient device cooling is employed). these currents can be reduced by: reducing the v cc - v ee operating voltage or by utilizing the v ext option. 12. when using v ext = 5.5v, current requirements of the v ext input can approach 100ma at maximum pattern rates. 13. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established b y characterization and are not production tested. test circuits and waveforms figure 1. driver switching test circuit figure 2. driver propagation delay and transition time measurement points electrical specifications test conditions: v cc = 12v, v ee = -3v, vh = 6v, vl = 0v, comp-high = 5v, comp-low = 0v, v 5v = v ee and lowswing = v cc . (continued) parameter symbol test conditions min typ max units v o data- drv en + drv en - vh vl dout data+ 1k 100pf note 8 v o 400mv 0v t pdlh v oh ( ? v h ) v ol ( ? v l ) 50% 50% t pdhl data- data+ t r t f data = 1 data = 0
isl55100a 7 fn7486.3 december 4, 2014 submit document feedback figure 3. driver enable and di sable time measurement points figure 4. receiver switching test circuit figure 5. receiver propagation delay measurement points test circuits and waveforms (continued) v o 400mv 0v t disl v ol ( ? v l ) 1v 10% t enh drv en - drv en + dis en (for data = 0) v ref v o v oh ( ? v h ) 2v 90% (for data = 1) v ref t dish t enl + - + - vinp qa qb comp hi comp lo cva cvb 5v qx 500mv -500mv t pdlh v oh ( ? 5v) v ol ( ? 0v) 50% 50% t pdhl vinp 0v 0v
isl55100a 8 fn7486.3 december 4, 2014 submit document feedback application information the isl55100a provides quad pin drivers and quad dual level comparator receivers in a small footprint. the four channels may be used as bidirectional or split channels. drivers have per channel level, data and high impedance controls, while comparators have per channel high and low threshold levels. receiver features the receivers are four independent window comparators that feature high output current capability, and user defined high and low output levels to interface with a wide variety of logic families. each receiver, comprises two comparators and each comparator has an independent threshold level input, making it easy to implement window comparator functions. the cva and cvb pins set the threshold levels of the a and b comparators respectively. comp high and comp low set all the comparator output levels, and comp high must be more positive than comp low. these two inputs are unbuffered supply pins, so the sources driving these pins must provide adequate current for the expected load. comp high and comp low typically connect to the power supplies of the logic device driven by the comparator outputs. the ?truth tabl e? for receivers is on page 3 . receiver outputs are not tri-statable, and do not incorporate any on-chip short-circuit current protection. momentary short circuits to gnd, or any supply voltage, won?t cause permanent damage, but care must be taken to avoid lo nger duration short circuits. if tolerable to the application, current limiting resistors can be inserted in series with the qa(0 to 3) and qb(0 to 3) outputs to protect the receiver outputs from damage due to overcurrent conditions. driver features the drivers are single-ended ou tputs featuring a wide voltage range, an output stage capable of delivering 200ma while providing a low out resistance and tri-state capability. additionally, the driver output can be toggled to drive one of two user defined output levels high (vh) or low (vl). driver waveforms are greatly affected by load characteristics. the isl55100a actually double bonds the vh(0 to 3) and vl(0 to 3) supply pins for each ch annel. the driver output pins (dout(0 to 3)) are triple bonded. multiple bond wires help reduce the effects of inductance between the ic die (wafer) and the packaging. also the qf n style of packaging reduces inductance over other types of packaging. while the inductance of a bond wire might seem insignificant, it can reduce high-frequency waveform fidelity. therefore, this should be borne in mind when doing pcb layout and dut interconnect. lead lengths should be kept as short as possible, maintaining as much decoupling on the drive rails as possible and make sure scope measurements are made properly. often the inductance of a scope prob e ground can be the actual cause of the waveform distortion. vh and vl (driver output rails) there are sets of vh and vl pins designated for each driver. these are unbuffered analog inputs that determine the drive high (vh) and drive low (vl) voltages that the drivers will deliver. these inputs are double bonded to reduce inductance and decrease ac impedance. each vh and vl should be decoupled with 4.7f and 0.1f capacitors to ground. if all four vh/vls are bussed per device then one 4.7f can be used for multiple vh/vl pins. layouts should also accommodate th e placement of capacitance ?across? vh and vl. so in addi tion to decoupling the vh/vl pins to ground, they are also decoupled to each other. logic inputs the isl55100a uses differential mode digital inputs, and can therefore mate directly with lvds or cml outputs. single-ended logic families are handled by connecting one of the digital input pins to an ap propriate threshold voltage (e.g., 1.4v for ttl compatibility). lowswing circuit option the drivers include switchable circuitry that is optimized for either low (vh - vl < 3v) or high output swings, and this selection is accomplished via the lowswing pin. connecting lowswing to vee selects the circ uits optimized for low overshoots at low swings, while tying the pin v cc enables the large signal circuitry (see figure 7 ). with lowswing = v ee , the low swing circuitry activates whenever vh < v ee + 5v, and the vh and vl currents increase, so for the lowest power dissipation set lowswing = v ee only if the output swing (vh - vl) is less than 3v, and better than 10% overshoots are required. for the best small signal performance, the vh/vl common mode voltage [(vh + vl)/2] must be v ee + 1.5v. so if v ee =0v, and the desired swing is 500mv, set vh = 1.75v, and vl = 1.25v. driver and receiver overload protection the isl55100a is designed to provide minimum and balanced driver r out . great care should be taken when making use of the isl55100a low r out drivers as there is no internal protection. there is no short-circ uit protection built into either the driver or the receiver/compa rator outputs. also there are no junction temperature monitors or thermal shutdown features. the driver or receiver outputs may be damaged by more than a momentary short-circuit directly to any low impedance voltage. if included, a 50 series termination resistor provides suitable driver protection, but should be properly rated. external logic su pply option (v ext ) connection of the v ext pin to a 5.5v dc source (referenced to v ee ) will reduce the v cc - v ee current drain. current drain is directly proportional to data rate. this option will help with power supply/dissipation should heat distribution become an issue. power supply bypassing and printed circuit board layout as with any high frequency device, good printed circuit board layout is necessary for optimu m performance. ground plane
isl55100a 9 fn7486.3 december 4, 2014 submit document feedback construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the vee pin is connected to ground, one 0.1f ceramic capacitor should be placed from the vcc pin to ground. a 4.7f tantalum capacitor should then be connected from the vcc pin to ground. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. power dissipation considerations specifying continuous data rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation/cooling necessities. driver output patterns also impact these needs. the faster the pin activity, the greater the need to supply current and remove heat. figures 17 and 18 address power consumption relative to frequency of operation. these graphs are based on driving 6.0/0.0v out into a 1k load. t ja for the device package is 23.0c/w, 16.6c/w and 14.9c/w based on airflows of 0m/s, 1m/s and 2.5m/s. the device is mounted per note 4 under ? thermal information ? on page 4 . with the high speed data rate capability of the isl55100a, it is possible to exceed the +150c ?absolute maximum junction temperature? as operating conditions and frequenc ies increase. therefore, it is important to calculate the maximum junction temperature for the application to determine if op erating conditions need to be modified for the device to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to equation 1 : where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the loads. power also depends on the number of cha nnels changing state, and the frequency of operation. the extent of continuous active pattern generation/reception will greatly effect dissipation requirements. the power dissipation curves ( figure 17 ), provide a way to see if the device will overheat. the junction temperature rise above ambient vs. operating frequency can be found graphically in figure 18 . this graph is based on the package type t ja ratings and actual current/wattage requirements of the isl55100a when driving a 1k load with a 6v high level and a 0v low rail. the temperatures are indicate d as calculated junction temperature over the ambient temperature of the user?s system. plots indicate temperature change as operating frequency increases (the graph assumes continuous operation). the user should eval uate various heat sink/cooling options in order to control the ambient temperature part of the equation. this is especially tr ue if the user?s applications require continuous, high speed operation. the reader is cautioned against assuming the same level of thermal performance in actual applications. a careful inspection of conditions in your application should be conducted. great care must be taken to ensure die temperature does not exceed absolute maximum thermal limits. important note: the isl55100a package metal pad (ep) is used for heat sinking of the devi ce. it is electrically connected to the negative supply potential (v ee ). if v ee is tied to ground, the thermal pad can be connecte d to ground. otherwise, the thermal pad (v ee ) must be isolated from other power planes. power supply sequencing the isl55100a references every supply with respect to v ee . therefore apply v ee , then v cc followed by the vh, vl busses, then the comp high and comp low followed by the cva and cvb supplies. digital inputs shou ld be set with a differential bias as soon as possible. in cases where v ext is being utilized (v ext = v ee + 5.5v), it should be po wered up immediately after v cc . basically, no pin shou ld be biased above v cc or below v ee . data rates please note that the frequency (mhz) in figures 17 and 18 contain two transitions within ea ch period. a digital application that requires a new test patt ern every 50ns would be running at a 20mhz data rate. figure 19 reveals that a 100ns period, 10mhz in frequency parlance, results in two 50ns digital patterns. esd protection figure 6 is the block diagram depicting the esd protection networks. the dout-to-vh diode is the upper fet?s drain-to-body diode. p dmax t jmax - t amax ? ja -------------------------------------------- - = (eq. 1)
isl55100a 10 fn7486.3 december 4, 2014 submit document feedback figure 6. esd structure block diagram
isl55100a 11 fn7486.3 december 4, 2014 submit document feedback typical performance curves device installed on intersil isl55100a evaluation board. figure 7. lowswing effects on driver shape and t pd (100pf-1k load) figure 8. driver waveforms under various loads figure 9. data/hiz/driver out timing figure 10. r out vs device voltage figure 11. r out vs vh rail figure 12. propagation delay vs vh rail, various loads 0 0 10ns/div 0.5v/div v cc 12.0 vh 2.0 v ee - 3.0 vl 0.0 lowswing off lowswing on 0.5v/div 0 0 10ns/div 2v/div v cc 12.0 vh 6.0 v ee - 3.0 vl 0.0 1k/100pf 680pf 1000pf 2200pf data in 0 0 20ns/div 2v/div drven data in driver out 0 v cc 12.0 vh 6.0 v ee - 3.0 vl 0.0 6 5 4 3 2 1 0 12 13 14 15 16 17 18 v cc - v ee volts (v ee - 3.0 fixed) vh (6.00v) r out : driver sources 200ma vl (0.0v) r out : driver sinks 200ma r out ( ) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 123456789101112131415 vh volts (vl = 0.0) vh (1v-15v) r out : driver sources 200ma vl (0.0v fixed) r out : driver sinks 200ma r out ( ? ) 20 18 16 14 12 10 8 6 4 2 0 1234567891011121314 vh volts (vl = 0.0) 2200pf 1000pf 680pf 1k/100pf t pd (ns)
isl55100a 12 fn7486.3 december 4, 2014 submit document feedback figure 13. driver fall time vs vh rail, various loads figure 14. driver and receiver tpd variance vs v cc figure 15. driver rise time vs vh rail, various loads figure 16. static i cc vs v cc figure 17. device powe r dissipation with v cc -v ee = 18, 12 and 9.0 (v ext = 5.5v) volts. all four pins making two transitions per period figure 18. calculated junction temp above ambient with v cc - v ee = 18, 12 and 9.0 (v ext = 5.5v) volts. all four pins making two transitions per period. typical performance curves device installed on intersil isl55100a evaluation board. (continued) 30 27 24 21 18 15 12 9 6 3 0 1234567891011121314 vh volts (vl = 0.0) 2200pf 1000pf 680pf 1k/100pf fall time (ns) 20 18 16 14 12 10 8 6 4 2 0 11 12 13 14 15 16 17 18 19 comparator t pd no load driver t pd no load t pd (ns) v cc -v ee (v ee = -3.0) 30 27 24 21 18 15 12 9 6 3 0 1234567891011121314 vh volts (vl = 0.0) 2200pf 1000pf 680pf 1k/100pf rise time (ns) 100 90 80 70 60 50 40 30 20 10 0 11 12 13 14 15 16 17 18 19 icc static conditions icc (ma) v cc -v ee (v ee = -3.0) 10 9 8 7 6 5 4 3 2 1 0 5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m 60m frequency (hz) 18v v cc 12v v cc 9v v cc and v ext = 5.5v power dissipation (w) 150 135 120 105 90 75 60 45 30 15 0 5 1015202530354045505560 frequency (mhz) airflow legend a = 0m/s : b = 1.0m/s : c = 2.5 m/s 18v v cc 12v v cc 9v v cc and v ext = 5.5v a b c a b c a b c temperature rise (c)
isl55100a 13 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7486.3 december 4, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support figure 19. frequency of 10mhz = 50ns pattern rate figure 20. minimum puls e width vh 6/8/10v revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change december 4, 2014 fn7489.3 update the datasheet throughout to intersil?s new standard. on page 2, updated the ordering information by adding msl note. on page 3, in ?pin descriptions? table, added ?this is also the potential of the exposed thermal pad on the package bottom.? to the vee row. added ?ep? row. on page 4, under ?absolute maximum ratings?changed ?dout? range from ?vl ? 0.5v? to ?vee - 0.5v?. on page 9, changed a sentence in the 5th paragraph from ?the maximum safe power temperature vs operating frequency can be found graphically in figure 18.? to ?the junction temperature rise above ambient vs. operating frequency can be found graphically in figure 18.? on page 9, edited ?esd protection? paragraph. on page 10, revised figure 6 to represent actual esd structures. on page 12, changed the y-axis label from ?temperature? to ?temperature rise?. added revision history and about intersil sections. typical performance curves device installed on intersil isl55100a evaluation board. (continued) 0 0 20ns/div 2v/div v cc + 6.0 vh 6.0 v ee - 3.0 vl 0.0 0 10ns/div 2v/div v cc 12.0 vh 6/8/10 v ee - 3.0 vl 0.0
isl55100a 14 fn7486.3 december 4, 2014 submit document feedback quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l72.10x10 72 lead quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - 0.02 0.05 - a2 - 0.65 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5, 8 d 10.00 bsc - d1 9.75 bsc 9 d2 5.85 6.00 6.15 7, 8 e 10.00 bsc - e1 9.75 bsc 9 e2 5.85 6.00 6.15 7, 8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8, 10 n722 nd 18 3 ne 18 3 p- -0.609 ? --129 rev. 1 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & ? are present when anvil singulation method is used and not present for saw singulation. 10. compliant to jedec mo-220vnnd-3 except for the "l" min dimension.

▲Up To Search▲

Price & Availability of ISL55100AEVAL3Z

	To Download ISL55100AEVAL3Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .